LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.dec_pkg.all;
entity dec_io is 
port(
		rst	   :in std_ulogic;
		clk_l 	   :in std_ulogic;               --clk_l low frequency, clk_h high frequency
		clk_r      :in std_ulogic;
		m1_en	   :in std_ulogic;		 --mem1
		cmd1       :in std_ulogic;               --mem1 (wr='1' | rd='0')
		addr1	   :in word16;			 --mem1	
		data1      :in word32;		 	 --mem1	
		wb_clk    :in std_ulogic;
		wb_en     :in std_ulogic;
		wb_addr   :in word16;
		wb_data   :in word16;
		m2_en	   :in std_ulogic;		 --mem2
		cmd2       :in std_ulogic;               --mem2 (wr='1' | rd='0')
		addr2	   :in word16;			 --mem2	
		debug_en : in std_ulogic;
                debug_sel : in std_ulogic;
		data2      :out word16;			 --mem2	
		ack2       :out std_ulogic;              --mem2
		ack1       :out std_ulogic;              --mem1
		irq        :out std_ulogic   ;            -- one frame ended (interruption);
                debug_clk : out std_ulogic;
                debug_data: out std_ulogic_vector(31 downto 0); 	
		LKDT       :out std_ulogic;
		N     : in std_ulogic_vector(3 downto 0);
		M     : in std_ulogic_vector(6 downto 0);
		OD    : in std_ulogic_vector(1 downto 0);
		BP    : in std_ulogic;		
		PDRST : in std_ulogic;

		rst_c	   :out std_ulogic;
		clk_l_c 	   :out std_ulogic;               --clk_l low frequency, clk_h high frequency
		clk_r_c      :out std_ulogic;
		m1_en_c	   :out std_ulogic;		 --mem1
		cmd1_c       :out std_ulogic;               --mem1 (wr='1' | rd='0')
		addr1_c	   :out word16;			 --mem1	
		data1_c      :out word32;		 	 --mem1	
		wb_clk_c    :out std_ulogic;
		wb_en_c     :out std_ulogic;
		wb_addr_c   :out word16;
		wb_data_c   :out word16;
		m2_en_c	   :out std_ulogic;		 --mem2
		cmd2_c       :out std_ulogic;               --mem2 (wr='1' | rd='0')
		addr2_c	   :out word16;			 --mem2	
		debug_en_c : out std_ulogic;
                debug_sel_c : out std_ulogic;
		data2_c      :in word16;			 --mem2	
		ack2_c       :in std_ulogic;              --mem2
		ack1_c       :in std_ulogic;              --mem1
		irq_c        :in std_ulogic   ;            -- one frame ended (interruption);
                debug_clk_c : in std_ulogic;
                debug_data_c : in std_ulogic_vector(31 downto 0); 	
		LKDT_c       :in std_ulogic;
		N_c     : out std_ulogic_vector(3 downto 0);
		M_c     : out std_ulogic_vector(6 downto 0);
		OD_c    : out std_ulogic_vector(1 downto 0);
		BP_c    : out std_ulogic;		
		PDRST_c : out std_ulogic
		);
end dec_io;
architecture rtl of dec_io is
       signal oen : std_ulogic;
       component PI  port (
         PAD :in std_ulogic;
         C :out  std_ulogic;
         IE :in  std_ulogic
       );
     end component;	
      component POT16  port (
         PAD :out std_ulogic;
         I :in std_ulogic;
         OEN :in std_ulogic
       );
     end component;
     component PO16  port (
         PAD :out  std_ulogic;
         I :in std_ulogic
       );
     end component;
     
begin	
	oen <= debug_sel;
 pi_rst : PI port map(PAD =>  rst, C =>  rst_c,IE => '1');
pi_clk_l : PI port map(PAD =>  clk_l, C =>  clk_l_c,IE => '1');
pi_clk_r : PI port map(PAD =>  clk_r, C =>  clk_r_c,IE => '1');
pi_m1_en : PI port map(PAD =>  m1_en, C =>  m1_en_c,IE => '1');
pi_cmd1 : PI port map(PAD =>  cmd1, C =>  cmd1_c,IE => '1');
pi_addr1_0 : PI port map(PAD =>  addr1(0), C =>  addr1_c(0),IE => '1');
pi_addr1_1 : PI port map(PAD =>  addr1(1), C =>  addr1_c(1),IE => '1');
pi_addr1_2 : PI port map(PAD =>  addr1(2), C =>  addr1_c(2),IE => '1');
pi_addr1_3 : PI port map(PAD =>  addr1(3), C =>  addr1_c(3),IE => '1');
pi_addr1_4 : PI port map(PAD =>  addr1(4), C =>  addr1_c(4),IE => '1');
pi_addr1_5 : PI port map(PAD =>  addr1(5), C =>  addr1_c(5),IE => '1');
pi_addr1_6 : PI port map(PAD =>  addr1(6), C =>  addr1_c(6),IE => '1');
pi_addr1_7 : PI port map(PAD =>  addr1(7), C =>  addr1_c(7),IE => '1');
pi_addr1_8 : PI port map(PAD =>  addr1(8), C =>  addr1_c(8),IE => '1');
pi_addr1_9 : PI port map(PAD =>  addr1(9), C =>  addr1_c(9),IE => '1');
pi_addr1_10 : PI port map(PAD =>  addr1(10), C =>  addr1_c(10),IE => '1');
pi_addr1_11 : PI port map(PAD =>  addr1(11), C =>  addr1_c(11),IE => '1');
pi_addr1_12 : PI port map(PAD =>  addr1(12), C =>  addr1_c(12),IE => '1');
pi_addr1_13 : PI port map(PAD =>  addr1(13), C =>  addr1_c(13),IE => '1');
pi_addr1_14 : PI port map(PAD =>  addr1(14), C =>  addr1_c(14),IE => '1');
pi_addr1_15 : PI port map(PAD =>  addr1(15), C =>  addr1_c(15),IE => '1');
pi_data1_0 : PI port map(PAD =>  data1(0), C =>  data1_c(0),IE => '1');
pi_data1_1 : PI port map(PAD =>  data1(1), C =>  data1_c(1),IE => '1');
pi_data1_2 : PI port map(PAD =>  data1(2), C =>  data1_c(2),IE => '1');
pi_data1_3 : PI port map(PAD =>  data1(3), C =>  data1_c(3),IE => '1');
pi_data1_4 : PI port map(PAD =>  data1(4), C =>  data1_c(4),IE => '1');
pi_data1_5 : PI port map(PAD =>  data1(5), C =>  data1_c(5),IE => '1');
pi_data1_6 : PI port map(PAD =>  data1(6), C =>  data1_c(6),IE => '1');
pi_data1_7 : PI port map(PAD =>  data1(7), C =>  data1_c(7),IE => '1');
pi_data1_8 : PI port map(PAD =>  data1(8), C =>  data1_c(8),IE => '1');
pi_data1_9 : PI port map(PAD =>  data1(9), C =>  data1_c(9),IE => '1');
pi_data1_10 : PI port map(PAD =>  data1(10), C =>  data1_c(10),IE => '1');
pi_data1_11 : PI port map(PAD =>  data1(11), C =>  data1_c(11),IE => '1');
pi_data1_12 : PI port map(PAD =>  data1(12), C =>  data1_c(12),IE => '1');
pi_data1_13 : PI port map(PAD =>  data1(13), C =>  data1_c(13),IE => '1');
pi_data1_14 : PI port map(PAD =>  data1(14), C =>  data1_c(14),IE => '1');
pi_data1_15 : PI port map(PAD =>  data1(15), C =>  data1_c(15),IE => '1');
pi_data1_16 : PI port map(PAD =>  data1(16), C =>  data1_c(16),IE => '1');
pi_data1_17 : PI port map(PAD =>  data1(17), C =>  data1_c(17),IE => '1');
pi_data1_18 : PI port map(PAD =>  data1(18), C =>  data1_c(18),IE => '1');
pi_data1_19 : PI port map(PAD =>  data1(19), C =>  data1_c(19),IE => '1');
pi_data1_20 : PI port map(PAD =>  data1(20), C =>  data1_c(20),IE => '1');
pi_data1_21 : PI port map(PAD =>  data1(21), C =>  data1_c(21),IE => '1');
pi_data1_22 : PI port map(PAD =>  data1(22), C =>  data1_c(22),IE => '1');
pi_data1_23 : PI port map(PAD =>  data1(23), C =>  data1_c(23),IE => '1');
pi_data1_24 : PI port map(PAD =>  data1(24), C =>  data1_c(24),IE => '1');
pi_data1_25 : PI port map(PAD =>  data1(25), C =>  data1_c(25),IE => '1');
pi_data1_26 : PI port map(PAD =>  data1(26), C =>  data1_c(26),IE => '1');
pi_data1_27 : PI port map(PAD =>  data1(27), C =>  data1_c(27),IE => '1');
pi_data1_28 : PI port map(PAD =>  data1(28), C =>  data1_c(28),IE => '1');
pi_data1_29 : PI port map(PAD =>  data1(29), C =>  data1_c(29),IE => '1');
pi_data1_30 : PI port map(PAD =>  data1(30), C =>  data1_c(30),IE => '1');
pi_data1_31 : PI port map(PAD =>  data1(31), C =>  data1_c(31),IE => '1');
pi_wb_clk : PI port map(PAD =>  wb_clk, C =>  wb_clk_c,IE => '1');
pi_wb_en : PI port map(PAD =>  wb_en, C =>  wb_en_c,IE => '1');
pi_wb_addr_0 : PI port map(PAD =>  wb_addr(0), C =>  wb_addr_c(0),IE => '1');
pi_wb_addr_1 : PI port map(PAD =>  wb_addr(1), C =>  wb_addr_c(1),IE => '1');
pi_wb_addr_2 : PI port map(PAD =>  wb_addr(2), C =>  wb_addr_c(2),IE => '1');
pi_wb_addr_3 : PI port map(PAD =>  wb_addr(3), C =>  wb_addr_c(3),IE => '1');
pi_wb_addr_4 : PI port map(PAD =>  wb_addr(4), C =>  wb_addr_c(4),IE => '1');
pi_wb_addr_5 : PI port map(PAD =>  wb_addr(5), C =>  wb_addr_c(5),IE => '1');
pi_wb_addr_6 : PI port map(PAD =>  wb_addr(6), C =>  wb_addr_c(6),IE => '1');
pi_wb_addr_7 : PI port map(PAD =>  wb_addr(7), C =>  wb_addr_c(7),IE => '1');
pi_wb_addr_8 : PI port map(PAD =>  wb_addr(8), C =>  wb_addr_c(8),IE => '1');
pi_wb_addr_9 : PI port map(PAD =>  wb_addr(9), C =>  wb_addr_c(9),IE => '1');
pi_wb_addr_10 : PI port map(PAD =>  wb_addr(10), C =>  wb_addr_c(10),IE => '1');
pi_wb_addr_11 : PI port map(PAD =>  wb_addr(11), C =>  wb_addr_c(11),IE => '1');
pi_wb_addr_12 : PI port map(PAD =>  wb_addr(12), C =>  wb_addr_c(12),IE => '1');
pi_wb_addr_13 : PI port map(PAD =>  wb_addr(13), C =>  wb_addr_c(13),IE => '1');
pi_wb_addr_14 : PI port map(PAD =>  wb_addr(14), C =>  wb_addr_c(14),IE => '1');
pi_wb_addr_15 : PI port map(PAD =>  wb_addr(15), C =>  wb_addr_c(15),IE => '1');
pi_wb_data_0 : PI port map(PAD =>  wb_data(0), C =>  wb_data_c(0),IE => '1');
pi_wb_data_1 : PI port map(PAD =>  wb_data(1), C =>  wb_data_c(1),IE => '1');
pi_wb_data_2 : PI port map(PAD =>  wb_data(2), C =>  wb_data_c(2),IE => '1');
pi_wb_data_3 : PI port map(PAD =>  wb_data(3), C =>  wb_data_c(3),IE => '1');
pi_wb_data_4 : PI port map(PAD =>  wb_data(4), C =>  wb_data_c(4),IE => '1');
pi_wb_data_5 : PI port map(PAD =>  wb_data(5), C =>  wb_data_c(5),IE => '1');
pi_wb_data_6 : PI port map(PAD =>  wb_data(6), C =>  wb_data_c(6),IE => '1');
pi_wb_data_7 : PI port map(PAD =>  wb_data(7), C =>  wb_data_c(7),IE => '1');
pi_wb_data_8 : PI port map(PAD =>  wb_data(8), C =>  wb_data_c(8),IE => '1');
pi_wb_data_9 : PI port map(PAD =>  wb_data(9), C =>  wb_data_c(9),IE => '1');
pi_wb_data_10 : PI port map(PAD =>  wb_data(10), C =>  wb_data_c(10),IE => '1');
pi_wb_data_11 : PI port map(PAD =>  wb_data(11), C =>  wb_data_c(11),IE => '1');
pi_wb_data_12 : PI port map(PAD =>  wb_data(12), C =>  wb_data_c(12),IE => '1');
pi_wb_data_13 : PI port map(PAD =>  wb_data(13), C =>  wb_data_c(13),IE => '1');
pi_wb_data_14 : PI port map(PAD =>  wb_data(14), C =>  wb_data_c(14),IE => '1');
pi_wb_data_15 : PI port map(PAD =>  wb_data(15), C =>  wb_data_c(15),IE => '1');
pi_m2_en : PI port map(PAD =>  m2_en, C =>  m2_en_c,IE => '1');
pi_cmd2 : PI port map(PAD =>  cmd2, C =>  cmd2_c,IE => '1');
pi_addr2_0 : PI port map(PAD =>  addr2(0), C =>  addr2_c(0),IE => '1');
pi_addr2_1 : PI port map(PAD =>  addr2(1), C =>  addr2_c(1),IE => '1');
pi_addr2_2 : PI port map(PAD =>  addr2(2), C =>  addr2_c(2),IE => '1');
pi_addr2_3 : PI port map(PAD =>  addr2(3), C =>  addr2_c(3),IE => '1');
pi_addr2_4 : PI port map(PAD =>  addr2(4), C =>  addr2_c(4),IE => '1');
pi_addr2_5 : PI port map(PAD =>  addr2(5), C =>  addr2_c(5),IE => '1');
pi_addr2_6 : PI port map(PAD =>  addr2(6), C =>  addr2_c(6),IE => '1');
pi_addr2_7 : PI port map(PAD =>  addr2(7), C =>  addr2_c(7),IE => '1');
pi_addr2_8 : PI port map(PAD =>  addr2(8), C =>  addr2_c(8),IE => '1');
pi_addr2_9 : PI port map(PAD =>  addr2(9), C =>  addr2_c(9),IE => '1');
pi_addr2_10 : PI port map(PAD =>  addr2(10), C =>  addr2_c(10),IE => '1');
pi_addr2_11 : PI port map(PAD =>  addr2(11), C =>  addr2_c(11),IE => '1');
pi_addr2_12 : PI port map(PAD =>  addr2(12), C =>  addr2_c(12),IE => '1');
pi_addr2_13 : PI port map(PAD =>  addr2(13), C =>  addr2_c(13),IE => '1');
pi_addr2_14 : PI port map(PAD =>  addr2(14), C =>  addr2_c(14),IE => '1');
pi_addr2_15 : PI port map(PAD =>  addr2(15), C =>  addr2_c(15),IE => '1');
pi_debug_en : PI port map(PAD =>  debug_en, C =>  debug_en_c,IE => '1');
pi_debug_sel : PI port map(PAD =>  debug_sel, C =>  debug_sel_c,IE => '1');
pi_N_0 : PI port map(PAD =>  N(0), C =>  N_c(0),IE => '1');
pi_N_1 : PI port map(PAD =>  N(1), C =>  N_c(1),IE => '1');
pi_N_2 : PI port map(PAD =>  N(2), C =>  N_c(2),IE => '1');
pi_N_3 : PI port map(PAD =>  N(3), C =>  N_c(3),IE => '1');
pi_M_0 : PI port map(PAD =>  M(0), C =>  M_c(0),IE => '1');
pi_M_1 : PI port map(PAD =>  M(1), C =>  M_c(1),IE => '1');
pi_M_2 : PI port map(PAD =>  M(2), C =>  M_c(2),IE => '1');
pi_M_3 : PI port map(PAD =>  M(3), C =>  M_c(3),IE => '1');
pi_M_4 : PI port map(PAD =>  M(4), C =>  M_c(4),IE => '1');
pi_M_5 : PI port map(PAD =>  M(5), C =>  M_c(5),IE => '1');
pi_M_6 : PI port map(PAD =>  M(6), C =>  M_c(6),IE => '1');
pi_OD_0 : PI port map(PAD =>  OD(0), C =>  OD_c(0),IE => '1');
pi_OD_1 : PI port map(PAD =>  OD(1), C =>  OD_c(1),IE => '1');
pi_BP : PI port map(PAD =>  BP, C =>  BP_c,IE => '1');
pi_PDRST : PI port map(PAD =>  PDRST, C =>  PDRST_c,IE => '1');

po_data2_0 : PO16 port map(PAD =>  data2(0), I =>  data2_c(0));
po_data2_1 : PO16 port map(PAD =>  data2(1), I =>  data2_c(1));
po_data2_2 : PO16 port map(PAD =>  data2(2), I =>  data2_c(2));
po_data2_3 : PO16 port map(PAD =>  data2(3), I =>  data2_c(3));
po_data2_4 : PO16 port map(PAD =>  data2(4), I =>  data2_c(4));
po_data2_5 : PO16 port map(PAD =>  data2(5), I =>  data2_c(5));
po_data2_6 : PO16 port map(PAD =>  data2(6), I =>  data2_c(6));
po_data2_7 : PO16 port map(PAD =>  data2(7), I =>  data2_c(7));
po_data2_8 : PO16 port map(PAD =>  data2(8), I =>  data2_c(8));
po_data2_9 : PO16 port map(PAD =>  data2(9), I =>  data2_c(9));
po_data2_10 : PO16 port map(PAD =>  data2(10), I =>  data2_c(10));
po_data2_11 : PO16 port map(PAD =>  data2(11), I =>  data2_c(11));
po_data2_12 : PO16 port map(PAD =>  data2(12), I =>  data2_c(12));
po_data2_13 : PO16 port map(PAD =>  data2(13), I =>  data2_c(13));
po_data2_14 : PO16 port map(PAD =>  data2(14), I =>  data2_c(14));
po_data2_15 : PO16 port map(PAD =>  data2(15), I =>  data2_c(15));
po_ack2 : PO16 port map(PAD =>  ack2, I =>  ack2_c);
po_ack1 : PO16 port map(PAD =>  ack1, I =>  ack1_c);
po_irq : PO16 port map(PAD =>  irq, I =>  irq_c);
po_LKDT : PO16 port map(PAD =>  LKDT, I =>  LKDT_c);

po_debug_clk :POT16 port map (PAD => debug_clk,
	                    I => debug_clk_c,
	                    OEN =>  oen);
po_debug_data_0 : POT16 port map(PAD =>  debug_data(0), I =>  debug_data_c(0),OEN => oen);
po_debug_data_1 : POT16 port map(PAD =>  debug_data(1), I =>  debug_data_c(1),OEN => oen);
po_debug_data_2 : POT16 port map(PAD =>  debug_data(2), I =>  debug_data_c(2),OEN => oen);
po_debug_data_3 : POT16 port map(PAD =>  debug_data(3), I =>  debug_data_c(3),OEN => oen);
po_debug_data_4 : POT16 port map(PAD =>  debug_data(4), I =>  debug_data_c(4),OEN => oen);
po_debug_data_5 : POT16 port map(PAD =>  debug_data(5), I =>  debug_data_c(5),OEN => oen);
po_debug_data_6 : POT16 port map(PAD =>  debug_data(6), I =>  debug_data_c(6),OEN => oen);
po_debug_data_7 : POT16 port map(PAD =>  debug_data(7), I =>  debug_data_c(7),OEN => oen);
po_debug_data_8 : POT16 port map(PAD =>  debug_data(8), I =>  debug_data_c(8),OEN => oen);
po_debug_data_9 : POT16 port map(PAD =>  debug_data(9), I =>  debug_data_c(9),OEN => oen);
po_debug_data_10 : POT16 port map(PAD =>  debug_data(10), I =>  debug_data_c(10),OEN => oen);
po_debug_data_11 : POT16 port map(PAD =>  debug_data(11), I =>  debug_data_c(11),OEN => oen);
po_debug_data_12 : POT16 port map(PAD =>  debug_data(12), I =>  debug_data_c(12),OEN => oen);
po_debug_data_13 : POT16 port map(PAD =>  debug_data(13), I =>  debug_data_c(13),OEN => oen);
po_debug_data_14 : POT16 port map(PAD =>  debug_data(14), I =>  debug_data_c(14),OEN => oen);
po_debug_data_15 : POT16 port map(PAD =>  debug_data(15), I =>  debug_data_c(15),OEN => oen);
po_debug_data_16 : POT16 port map(PAD =>  debug_data(16), I =>  debug_data_c(16),OEN => oen);
po_debug_data_17 : POT16 port map(PAD =>  debug_data(17), I =>  debug_data_c(17),OEN => oen);
po_debug_data_18 : POT16 port map(PAD =>  debug_data(18), I =>  debug_data_c(18),OEN => oen);
po_debug_data_19 : POT16 port map(PAD =>  debug_data(19), I =>  debug_data_c(19),OEN => oen);
po_debug_data_20 : POT16 port map(PAD =>  debug_data(20), I =>  debug_data_c(20),OEN => oen);
po_debug_data_21 : POT16 port map(PAD =>  debug_data(21), I =>  debug_data_c(21),OEN => oen);
po_debug_data_22 : POT16 port map(PAD =>  debug_data(22), I =>  debug_data_c(22),OEN => oen);
po_debug_data_23 : POT16 port map(PAD =>  debug_data(23), I =>  debug_data_c(23),OEN => oen);
po_debug_data_24 : POT16 port map(PAD =>  debug_data(24), I =>  debug_data_c(24),OEN => oen);
po_debug_data_25 : POT16 port map(PAD =>  debug_data(25), I =>  debug_data_c(25),OEN => oen);
po_debug_data_26 : POT16 port map(PAD =>  debug_data(26), I =>  debug_data_c(26),OEN => oen);
po_debug_data_27 : POT16 port map(PAD =>  debug_data(27), I =>  debug_data_c(27),OEN => oen);
po_debug_data_28 : POT16 port map(PAD =>  debug_data(28), I =>  debug_data_c(28),OEN => oen);
po_debug_data_29 : POT16 port map(PAD =>  debug_data(29), I =>  debug_data_c(29),OEN => oen);
po_debug_data_30 : POT16 port map(PAD =>  debug_data(30), I =>  debug_data_c(30),OEN => oen);
po_debug_data_31 : POT16 port map(PAD =>  debug_data(31), I =>  debug_data_c(31),OEN => oen);


end rtl;	

